Impact of post-metal deposition annealing temperature on performance and reliability of high-K metal-gate n-FinFETs

Publication date: 1 December 2016
Source:Thin Solid Films, Volume 620
Author(s): Chien-Yu Lin, Ting-Chang Chang, Kuan-Ju Liu, Jyun-Yu Tsai, Ching-En Chen, Hsi-Wen Liu, Ying-Hsin Lu, Tseung-Yuen Tseng, Osbert Cheng, Cheng-Tung Huang
This research studies the effects of post-metal deposition annealing temperature on degradation induced by positive bias stress (PBS) in TiN/HfO2 n-channel fin field-effect transistors (FinFETs). The initial electrical characteristics possess higher threshold voltage, transconductance and on-state current in high-annealing temperature devices. In addition, PBS-induced degradation was found to be more severe in high-annealing temperature devices due to more high-k bulk traps. However, in these devices, oxygen vacancies are generated within HfO2 since oxygen is more likely to diffuse toward the interface layer (IL) and repair Si/SiO2 dangling bonds. Furthermore, using charge-pumping and C–V measurements, less interface trapping and a thicker IL were found in high-annealing temperature devices, verifying the proposed model.